Integrated circuits are used for varieties of products, and many integrated circuits include complicated combinational logic circuits. Such combination logic is often tested with LSSD. LSSD uses sequential scan latches having a shift function to test the combinational circuits, in which a test pattern is scanned in to the combinational circuits and a resultant pattern is scanned out, with scan-in and scan-out controlled by controlled by a clock signal.
To test the combinational logic at the operating frequency, test data is loaded into the scan latches using a scan clock but transfer across the combinational logic from a sending latch to a receiving latch using a clock running at the operational frequency of the combinational logic (the scan clock has a frequency lower than the operational frequency). When, LSSD testing is performed at the operating frequency of the combinational logic using scan latch chains that cross two or more time domains, each running at a different operational frequency, a problem arises of synchronizing data transfer from the last latch in the first time domain to a first latch in the second time domain at the boundary where the scan chain crosses the different time domains. Therefore, there is a need for method and circuit for synchronizing data transfer from the last latch in the first time domain to a first latch in the second time domain when a scan chain crosses different time domains.